1. Field of the Invention:
The present invention relates to a bitline precharge circuit for a semiconductor memory device, and more particularly relates to a bitline precharge circuit for precharging the bitlines connected to memory cells arranged in matrix.
2. Description of the Related Art:
An exemplary configuration of a conventional SRAM (static random access memory) is shown in FIG. 10. In this SRAM, multiple word lines WL and multiple bitline pairs BIT and /BIT are arranged in the row direction and the column direction, respectively. The same number of memory cells MRC as the number of the rows are connected to each bitline pair BIT and /BIT associated with each column Col. These memory cells MRC connected to a bitline pair BIT and /BIT on an identical column Col are connected to respectively different word lines WL, while the memory cells MRC which are connected to bitline pairs BIT and /BIT on different columns Col and disposed on the row are connected to one and the same word line WL. For the sake of simplifying the description, it should be noted that FIG. 10 illustrates only two word lines WL.sub.1 and WL.sub.2 corresponding to two rows, only two bitline pairs BIT.sub.1 & /BIT.sub.1 and BIT.sub.2 & /BIT.sub.2 corresponding to two columns Col.sub.1 and Col.sub.2, only two memory cells MRC.sub.1 and MRC.sub.2 connected to the bitline pair BIT.sub.1 and /BIT.sub.1 on the first column Col.sub.1 and only two memory cells MRC.sub.3 and MRC.sub.4 connected to the bitline pair BIT.sub.2 and /BIT.sub.2 on the second column Col.sub.2. As shown in FIG. 10, the memory cells MRC.sub.1 and MRC.sub.3 on the same row are connected to the same word line WL.sub.1 and the memory cells MRC.sub.2 and MRC.sub.4 on the same row are connected to the same word line WL.sub.2.
The pair of bitlines BIT.sub.1 and /BIT.sub.1 on the first column Col.sub.1 are connected to data lines D.sub.1 and /D.sub.1, respectively, via associated column selector circuits 3 on the first column Col.sub.1, while the pair of bitlines BIT.sub.2 and /BIT.sub.2 on the second column Col.sub.2 are connected to data lines D.sub.2 and /D.sub.2, respectively, via associated column selector circuits 3 on the second column Col.sub.2. Each of the column selector circuits 3 is a circuit for connecting the bitlines BIT and /BIT to the data lines D.sub.1 and /D.sub.1 or D.sub.2 and /D.sub.2 via a single N-MOSFET (N-channel metaloxide-semiconductor field effect transistor) N.sub.11, the ON/OFF states of which are controlled by a column select signal Y. It is noted that the column select signal Y is a control signal for selecting a specified column Col and that different column select signals Y are used for the respective columns Col. Specifically, the pair of column selector circuits 3 on the first column Col.sub.1 are controlled by a column select signal Y.sub.1 on the same first column Col.sub.1, while the pair of column selector circuits 3 on the second column Col.sub.2 are controlled by a column select signal Y.sub.2 on the same second column Col.sub.2. Herein, the data line pair D.sub.1 and /D.sub.1 are connected to the bitline pair BIT.sub.1 and /BIT.sub.1 adjacent thereto and the data line pair D.sub.2 and /D.sub.2 are connected to the bitline pair BIT.sub.2 and /BIT.sub.2 adjacent thereto.
The bitline pair BIT.sub.1 and /BIT.sub.1 on the first column Col.sub.1 are connected to a power supply V.sub.cc via associated bitline precharge circuits 1 on the first column Col.sub.1, while the bitline pair BIT.sub.2 and /BIT.sub.2 on the second column Col.sub.2 are connected to the power supply V.sub.cc via associated bitline precharge circuits 1 on the second column Col.sub.2. Each of the bitline precharge circuits 1 is constituted by a single NMOS transistor N.sub.1 shown in FIG. 11, in which the drain D thereof is connected to the power supply V.sub.cc, the source S thereof is connected to the associated bitline BIT or /BIT and a precharge signal EQ.sub.0 is input to the gate G thereof. Thus, each bitline precharge circuit 1 connects the bitline BIT or /BIT to the power supply V.sub.cc when the precharge signal EQ.sub.0 is at an H level (equal to the level of the power supply voltage V.sub.cc). Moreover, as shown in FIG. 10, a pair of bitlines BIT and /BIT on each column Col are connected to each other via an NMOS transistor N.sub.12, the ON/OFF states of which are controlled by the precharge signal EQ.sub.0. It is noted that the precharge signal EQ.sub.0 is a control signal commonly used among the respective columns Col.
In the SRAM having such a configuration, during a precharge period before a write operation or a read operation is performed, the precharge signal EQ.sub.0 rises to the H level, thereby connecting all the bitline pairs BIT and /BIT to the power supply V.sub.cc via the NMOS transistors N.sub.1 of the bitline precharge circuits 1. However, since the ON state of the NMOS transistor N.sub.1 cannot be maintained unless the potential difference between the gate G and the source S thereof is equal to or larger than a threshold voltage Vth, the potential on the bitline pair BIT and /BIT can only be charged up to a voltage which is lower than the power supply voltage V.sub.cc by the threshold voltage Vth and which becomes a precharge level. This NMOS transistor N.sub.1 has a high threshold voltage Vth because of the influence of a substrate bias and the like. For example, assuming that the power supply voltage V.sub.cc is 4 V, the threshold voltage Vth becomes about 1.5 V. Thus, the precharge level becomes equal to about 2.5 V, which is an approximately intermediate voltage between the power supply voltage V.sub.cc of 4 V and the voltage of a ground GND of 0 V. Furthermore, when the precharge signal EQ.sub.0 rises to the H level, a pair of bitlines BIT and /BIT on each column Col are connected to each other via the NMOS transistor N.sub.12 so that the voltages or the precharge levels of the bitlines BIT and /BIT are equalized.
It is noted that the terms "power supply" and "ground" mean a pair of powers having such a relationship that the potential difference obtained by subtracting the ground voltage from the power supply voltage always becomes positive.
When the precharging of all the bitlines BIT and /BIT is completed in the above-described manner, a row is selected by activating any of the word lines WL (setting the word line WL at the H level, for example) and at the same time, a column Col is selected by setting any of the column select signals Y at the H level, thereby writing the data input to a pair of data lines D.sub.1 and /D.sub.1 or D.sub.2 and /D.sub.2 to the memory cell MRC on the selected row via the pair of bitlines BIT and /BIT on the selected column Col or outputting the data read out from the memory cell MRC through the pair of data lines D.sub.1 and /D.sub.1 or D.sub.2 and /D.sub.2 via the pair of bitlines BIT and /BIT.
On the other hand, if any of the word lines WL is activated during such a write operation or read operation, the memory cells MRC on all the columns Col which are disposed on the row corresponding to the activated word line WL are connected to the associated bitline pairs BIT and /BIT. Thus, if data which has been written or read during a previous write or read operation remains on these bitlines BIT and /BIT, then it takes a long time to read out the data stored in the memory cells MRC, or in some cases, the data may be possibly destroyed. Thus, before the write operation or the read operation is performed, all the bitlines BIT and /BIT are required to be precharged to the precharge level intermediate between the power supply voltage V.sub.cc and the ground voltage GND by using the bitline precharge circuits 1.
However, as shown in FIG. 10, a parasitic capacitance C is generated between the bitline /BIT.sub.1 on the first column Col.sub.1 and the bitline BIT.sub.2 on the second column Col.sub.2 which are adjacent to each other, for example. Thus, when the potential of the bitline /BIT.sub.1 on the selected column Col.sub.1 is abruptly varied by the input of data during a write operation, the precharge level on the non-selected bitline BIT.sub.2 adjacent to the bit-line /BIT.sub.1 is sometimes varied considerably, owing to a coupling (or an electrostatic induction) caused by the parasitic capacitance C. As the gap between adjacent bitlines BIT and /BIT becomes finer for fulfilling the requirements of downsizing a chip and increasing the storage capacity, the parasitic capacitance C generated therebetween increases correspondingly. As a result, the influence of the coupling is also increased. However, during a read operation, since the potential on the bitline BIT.sub.1 is slightly varied, the influence of the coupling is relatively small.
In this case, if a memory cell MRC is of a C-MOS (complementary MOS) type, a bitline pair BIT and /BIT can be rapidly charged from such a memory cell MRC. Thus, the potential variation on a non-selected bitline BIT or /BIT resulting from the coupling caused by the parasitic capacitance C is substantially negligible. However, in the SRAM, in order to downsize a chip and improve the response characteristics thereof, a memory cell MRC of a high-resistance pull-up type or a high-resistance pull-down type is often used.
As shown in FIG. 12, a high-resistance pull-up type memory cell MRC includes two NMOS transistors N.sub.21, and N.sub.22. The drains D of the NMOS transistors N.sub.21 and N.sub.22 are connected to a power supply V.sub.cc via high resistances R.sub.1 and R.sub.2, respectively. The sources S of the NMOS transistors N.sub.21 and N.sub.22 are connected to a ground GND. And the gates G of the NMOS transistors N.sub.21 and N.sub.22 are connected to the drains D of the other NMOS transistors N.sub.22 and N.sub.21, respectively. The drains D of these NMOS transistors N.sub.21 and N.sub.22 are also connected to a pair of bitlines BIT and /BIT via NMOS transistors N.sub.23 and N.sub.24 or switching elements (the gates of which are connected to a word line WL), respectively. Thus, in this high-resistance pull-up type memory cell MRC, in the situation where the word line WL rises to the H level and whereby the NMOS transistors N.sub.23 and N.sub.24 are turned ON, if the potential on a bitline BIT is too low, then it takes a long time to charge the bitline BIT from the power supply V.sub.cc via the high resistance R.sub.1, even when the drain D of the NMOS transistor N.sub.21 holds an H level state, for example. As a result, in the meantime, the potential of the gate G of the NMOS transistor N.sub.22 may become low so that the NMOS transistor N.sub.22 may be inverted from ON into OFF. Consequently, the data stored in the NMOS transistor N.sub.22 is possibly destroyed. In other words, in the case of using such a high-resistance pull-up type memory cell MRC, if the potential on a non-selected bitline BIT or /BIT becomes low because of the coupling caused by the parasitic capacitance C, then the data stored therein is more likely to be destroyed.
In the configuration shown in FIG. 10, assuming that the potential variation on a selected bitline /BIT.sub.1 is denoted by .DELTA.Vb1 and the parasitic grounded capacitance of the bitline BIT.sub.2 adjacent to the bitline /BIT.sub.1 is denoted by Cb2 (C is a parasitic capacitance therebetween), the potential variation .DELTA.Vb2 on the bitline BIT.sub.2 can be represented as: EQU .DELTA.Vb2=.DELTA.Vb1.multidot.C/Cb2
In addition, assuming that the inversion potential of the high-resistance pull-up type memory cell MRC shown in FIG. 12 is denoted by Vm, the potential V on the adjacent non-selected bitline BIT.sub.2 is required to satisfy the following relationship: EQU V&gt;Vm+.DELTA.Vb2
Thus, during a write operation, when the word line WL.sub.1 and the column select signal Y.sub.1 rise to the H level and the input of data to the bitline /BIT.sub.1 largely lowers the potential on the bitline /BIT.sub.1, for example, the potential V on the non-selected bitline BIT.sub.2 adjacent to the bitline /BIT.sub.1 is also lowered because of the coupling. Thus, if the potential V on the bitline BIT.sub.2 becomes equal to or lower than Vm+AVb2, then the data stored in the memory cell MRC.sub.3 is destroyed.
For example, assume a case shown in FIG. 13. As shown in FIG. 13, when the precharging is completed at a time t.sub.11 by the fall of the precharge signal EQ.sub.0 to the L level (i.e., the voltage level of the ground GND=0 V), the potential on a selected bitline pair BIT.sub.1 and /BIT.sub.1 has reached a normal precharge level or the voltage V.sub.2 (about 2.4 V), whereas the potential on a nonselected bitline pair BIT.sub.2 and /BIT.sub.2 has reached only the voltage V.sub.1 (about 2.25 V) lower than the voltage V.sub.2 because of the influence of the previous access. When the word line WL.sub.1 rises to the H level at a time t.sub.12, the potential on one /BIT.sub.1 of the selected bitline pair once increases because of the influence of the previous access and then decreases considerably to the vicinity of 0 V.
In such a case, the potential on one BIT.sub.2 of the non-selected bitline pair which is adjacent to the bitline /BIT.sub.1 also increases slightly once, and then decreases considerably. Consequently, at a time t.sub.13, the voltage levels at internal nodes ND.sub.1 and ND.sub.2 of the memory cell MRC.sub.3 are inverted so that the data stored therein is destroyed.
On the other hand, a high-resistance pull-down type memory cell MRC includes two PMOS transistors (or P-channel MOSFETs) P.sub.21 and P.sub.22, as shown in FIG. 14. The sources S of the PMOS transistors P.sub.21 and P.sub.22 are connected to a power supply V.sub.cc. The drains D of the PMOS transistors P.sub.21 and P.sub.22 are connected to a ground GND via high resistances R.sub.1 and R.sub.2, respectively. And the gates G of the PMOS transistors P.sub.21 and P.sub.22 are connected to the drains D of the other PMOS transistors P.sub.22 and P.sub.21, respectively. The drains D of these PMOS transistors P.sub.21 and P.sub.22 are also connected to bitlines BIT and /BIT via NMOS transistors N.sub.23 and N.sub.24 (the gates of which are connected to a word line WL), respectively. Thus, in this high-resistance pull-down type memory cell MRC, in the situation where the word line WL rises to the H level and whereby the NMOS transistors N.sub.23 and N.sub.24 are turned ON, if the potential on a bitline BIT is too high, then it takes a long time to discharge from the bitline BIT to the ground GND via the high resistance R.sub.1, even when the drain D of the PMOS transistor P.sub.21 holds an L level state, for example. As a result, in the meantime, the potential on the gate G of the PMOS transistor P.sub.22 may increase so that the PMOS transistor P.sub.22 may be inverted from ON into OFF. Consequently, the data stored in the PMOS transistor P.sub.22 is possibly destroyed. In other words, in the case of using such a high-resistance pull-down type memory cell MRC, if the potential on a non-selected bitline BIT or /BIT increases because of the coupling caused by the parasitic capacitance C, then the data stored therein is more likely to be destroyed.
Thus, in a conventional SRAM, if the potential on a selected bitline pair BIT and /BIT is largely varied by the input of data, then the potential precharged on an adjacent bitline pair BIT and /BIT is also varied because of the coupling caused by the parasitic capacitance C. Consequently, such an SRAM has problem in that the data stored in a non-selected memory cell MRC on the adjacent bitline pair BIT and /BIT is possibly destroyed.
In order to solve such a problem, it has conventionally been proposed to provide electrostatic shielding wires, to which the ground GND is always connected, between two adjacent bitlines BIT and /BIT. However, in order to provide such electrostatic shielding wires, the gap between adjacently disposed bitlines BIT and /BIT must be widened. As a result, a new problem is caused in that it becomes difficult to fulfill the requirement of downsizing a chip.